1. Field of the Invention
The present invention relates to a MOS field-effect transistor having silicon on insulator (SOI) structure.
2. Description of the Related Art
In recent years, with the explosive expansion of the Internet and advancement of a multimedia information society, a mobile information terminal market has been growing remarkably. There is a demand for further miniaturization and reduction in power consumption of information devices or LSIs constituting the information devices. As a device technique for meeting the demand, an SOI device has been focused. When a MOS transistor is formed on a semiconductor substrate having an SOI structure, as compared with a conventional bulk Si device, it is advantageous in terms of reduction in a parasitic capacitance such as a junction capacitance and a wiring capacitance, a low substrate bias effect, suppress of a short channel effect, perfect device isolation, a steep subthreshold characteristic, and the like. As a result, a large effect of low power consumption and high performance of the LSI can be exerted.
However, there is a technical problem in the SOI type MOS transistor. When a local oxidation of silicon (LOCOS) process is applied to element isolation, a thin silicon active layer is formed at a LOCOS isolation edge, thereby leading to formation of a parasitic MOS transistor having a low threshold voltage, and such a characteristic as to exhibit a hump shape (hereinafter, referred to simply as “hump”) may be caused in an Id-Vg characteristic. The hump is likely to generate in an NMOS and leads to a leak current.
As means for preventing the generation of the hump, for example, JP 08-181316 A proposes a method of forming a high concentration impurity on a substrate provided immediately below the LOCOS isolation edge or on the entire surface of the substrate, and JP 2000-306994 A proposes a method of changing a shape of the LOCOS isolation edge. Further, as another means for preventing the generation of the hump, JP 2001-148481 A discloses a method of lowering a temperature to 800° C. in an atmosphere of oxygen after LOCOS oxidation and then taking out a wafer from an oxidation furnace, thereby suppressing the generation of the hump with a greater use of fixed charges.
However, in these methods there is a problem that processes such as ion implantation and annealing are additionally employed in the method of JP 08-181316 A, processes are complicated in the method of JP 2000-306994 A, and that only a small effect can be obtained in NMOS or CMOS in the method of JP 2001-148481 A.